Logic Design and Verification Using SystemVerilog Donald Thomas 9781500385781 Books
Download As PDF : Logic Design and Verification Using SystemVerilog Donald Thomas 9781500385781 Books
Note This book has been replaced by a new edition titled "Logic Design and Verification Using SystemVerilog (Revised)" with ISBN 978-1523364022. Search for it here on . In other words, don't buy this out-of-date version of the book, go for the newer version.
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at • students currently in an introductory logic design course that also teaches SystemVerilog, • designers who want to update their skills from Verilog or VHDL, and • students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design — these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book’s topics. The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.
Logic Design and Verification Using SystemVerilog Donald Thomas 9781500385781 Books
It's a okay introductory book that has at least a few flaws:1. Chapter questions do not have easily-attainable solutions, at least from what I can read. This arguably makes it much more of classroom textbook, rather than a designer's reference. If anyone knows where I can find them, let me know and I'll modify my review. Other than that, assume you'll need a teachers' guide for the solutions.
2. Very little mention of code safety, and promotion of using casex, which many design shops would agree should never be used in hardware due to risk of masking X's. I wouldn't want the engineers on my team to be using this as their primary reference.
3. Generally has a difficult-to-follow flow through the book. As someone who is very well versed in the concepts that are being discussed, I found myself having to re-read several sections just to extract the point that the author is trying to make.
Fortunately for this book, there's not a lot of competition out there for SystemVerilog references. But as soon as some better ones are published, this one should fall to the bottom of the ranking.
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Tags : Logic Design and Verification Using SystemVerilog [Donald Thomas] on Amazon.com. *FREE* shipping on qualifying offers. Note: This book has been replaced by a new edition titled Logic Design and Verification Using SystemVerilog (Revised) with ISBN 978-1523364022. Search for it here on Amazon. In other words,Donald Thomas,Logic Design and Verification Using SystemVerilog,CreateSpace Independent Publishing Platform,1500385786,Logic Design,Computer Books: General,Computers,Computers Logic Design
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Logic Design and Verification Using SystemVerilog Donald Thomas 9781500385781 Books Reviews
This is an excellent, up-to-date book. There are plenty of clear, tutorial-style explanations, with equal emphasis on logic design, verification, and the SystemVerilog language. It's the best book I've found so far on these subjects. I'm guessing that Prof. Thomas certainly could have published this book with one of the major scientific publishers, but that he chose to publish using CreateSpace so that the price could be kept reasonable. In any case, the book is physically fine.
It's a okay introductory book that has at least a few flaws
1. Chapter questions do not have easily-attainable solutions, at least from what I can read. This arguably makes it much more of classroom textbook, rather than a designer's reference. If anyone knows where I can find them, let me know and I'll modify my review. Other than that, assume you'll need a teachers' guide for the solutions.
2. Very little mention of code safety, and promotion of using casex, which many design shops would agree should never be used in hardware due to risk of masking X's. I wouldn't want the engineers on my team to be using this as their primary reference.
3. Generally has a difficult-to-follow flow through the book. As someone who is very well versed in the concepts that are being discussed, I found myself having to re-read several sections just to extract the point that the author is trying to make.
Fortunately for this book, there's not a lot of competition out there for SystemVerilog references. But as soon as some better ones are published, this one should fall to the bottom of the ranking.
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